Real World Multicore Embedded Systems

This Expert Guide gives you the techniques and technologies in embedded multicore to optimally design and implement your embedded system. Written by experts with a solutions focus, this encyclopedic reference gives you an indispensable aid to tackling the day-to-day problems when building and managing multicore embedded systems. Following an embedded system design path from start to finish, our team of experts takes you from architecture, through hardware implementation to software programming and debug. With this book you will learn: • What motivates multicore • The architectural options and tradeoffs; when to use what • How to deal with the unique hardware challenges that multicore presents • How to manage the software infrastructure in a multicore environment • How to write effective multicore programs • How to port legacy code into a multicore system and partition legacy software • How to optimize both the system and software • The particular challenges of debugging multicore hardware and software Examples demonstrating timeless implementation details Proven and practical techniques reflecting the authors’ expertise built from years of experience and key advice on tackling critical issues

Unlike general-purpose computing systems, multicore embedded systems are designed with a specific application in mind. The memory access patterns for the application can be used to customize the memory architecture of the device. This chapter presents a synopsis of memory types and architecture commonly used in multicore embedded systems. It examines the many trade-offs that can be considered when designing the memory architecture. It considers factors such as whether the memory should be shared or distributed among the multiple cores; will the cores benefit from memory cache and what should the cache configuration be; is there a cache coherency protocol used; should there be other memory types on the device such as scratch pad SRAMs and eDRAMs; does the device use a DMA for memory transfers, and other factors. It provides guidance to the embedded system designers to tailor the memory architecture to their needs.

As in any complex architecture, debug and instrumentation resources are critical for multicore design. Debug instrumentation provides information for post-silicon debug analysis, software optimization, and performance monitoring. In this chapter, we introduce debug concepts useful for multicore; we deconstruct and discuss different debug instrumentation blocks and interfaces, including typical operations and system integration; and we discuss differences, considerations, and approaches more appropriate to multicore debug. This is followed by multicore debug examples, some of which are based on open standards and some on commercially-available blocks from processor IP providers.

This chapter discusses the potential of and role of system virtualization in meeting the flexibility, scalability, portability, and robustness demands of next-generation multicore embedded systems. Common architectural approaches to hypervisors are compared, including a strong focus on effective sharing and management of I/O peripherals across virtual machines. The chapter also describes and contrasts the virtualization hardware assistance features available in common multicore processors. Finally, emerging applications and use cases enabled by system virtualization are provided.

Synchronization hardware is a fundamental requirement for concurrent software. Ultimately, software depends upon strong guarantees for atomicity, which can only be provided by hardware. Fortunately, hardware can provide a simple but powerful programming interface to higher-level software using only a few synchronization primitives. These few primitives can support a surprisingly broad range of capabilities in software. Yet, even with hardware support to ensure functional correctness, there is an unavoidable performance overhead to pay for synchronization. In recent years, hardware designed to replace precise locking with speculative lock avoidance (e.g., lock-free programming) has begun to emerge. This chapter provides an in-depth look at the lowest level hardware/software interface for synchronization, along with explanations of how the underlying hardware ensures atomicity, and considerations related to weakly consistent memory models. This is complemented with a discussion of various lock avoidance techniques.

Growth in the number of transistors per die of an integrated circuit has provided impetus to the development of system-on-chip microprocessors (SoCs). They are becoming ubiquitous and appear in home appliances, cell phones, tablet, laptop, and desk-top computers, and lately even as building blocks in high-end computer systems. As the semiconductor manufacturing technology progresses in concert with Moore’s law, SoCs clearly represent the trend of the future of microprocessor design. SoCs vary widely in composition, complexity and sophistication depending on the computing applications for which they are intended: some are simple single-processor systems, while others range from a few to a few tens of processor cores and contain other hardware functional blocks, storage elements, memory controllers and interfaces to external high-speed interconnections such as PCI Express, SRIO, and others. In any such SoC, the on-chip interconnections play a central role in its operation and contribute vitally to the performance of the applications running in it. This chapter explores the choices of interconnections that may be employed and discusses the criteria for their selection. The chapter illustrates the interconnection selection process by describing an example SoC and examining the interconnections it contains.

Some embedded systems require so much performance that they cannot tolerate the overhead imposed by an operating system. Such systems can be built with little to no operating system services, and are often referred to as “bare-metal” systems. Because most programming techniques rely on system services, bare-metal programming requires a different way of implementing code on a multicore platform. This chapter describes where bare-metal systems are used, those aspects that differentiate them from more standard systems, and how they can be designed and programmed.

Synchronization is the key mechanism used within software applications to safely and efficiently leverage today’s multicore hardware architectures. This chapter aims to build your expertise and knowledge in software synchronization, from the needs behind synchronization to the possible solutions to implement synchronization. The target reader of this chapter is the embedded multicore software developer, along with the tester, project manager, and customer, in order to educate the entire software development team about the technology and the issues. Problems that occur when synchronization is not used, or when it is used badly, are considered. An in-depth look at how to achieve synchronization and also specific conditions that require synchronization are the primary focus of this chapter. Specific synchronization support for different languages, along with design patterns useful for architecting of a synchronized system, are discussed. The chapter wraps up looking at side-effects (good and bad) and problems encountered when writing synchronization code, as well as hardware and operating system effects on synchronization.

Efficient software development requires adequate toolsets to assist the developer in analyzing and optimizing a software application’s performance. With the relatively recent advent of multicore embedded hardware platforms, toolsets for supporting multicore development have appeared, although, in some cases, capabilities may be missing or immature, leaving software developers to manually massage outputs from one tool into inputs for the next tool or struggling to investigate unexpected multicore behaviors. This section reviews those multicore tools currently available for software developers as well as those that are still needed for adequate support.

This chapter discusses communication and synchronization libraries which can be used to implement parallelism in your embedded application. Details will be shared on several common libaries including Windows Threads, POSIX Threads, Threading Building Blocks, OpenMP, and MCAPI.

This chapter will introduce the concepts of multicore related issues, while the subsequent chapters will go into further details. We will start with a general analysis of how electronic design trends lead to multicore hardware-software architectures as the only viable solution addressing consumer requirements on cost, performance and power. We will then categorize multicore architecture concepts by processing and communication requirements and show how different processing techniques combine to form multicore architectures that address the specific needs of different application domains. Special attention will be given to the programmability of the different hardware architectures and the impact that hardware has on software. We will close the chapter with a brief review of existing hardware architectures available on the market, as well as a brief discussion about programming models capable of expressing parallel functionality, which can then be mapped into multiple processor cores.

An operating system (OS) is an important component of most computer systems. At a minimum, the OS is responsible for managing tasks and resources. This becomes more challenging in a multicore environment, where multiple tasks can execute concurrently and must vie for shared resources. So the OS configuration is a critical consideration when building a multicore system. This chapter describes the different ways one or more OSes can be instantiated in multicore systems, along with many of the more critical controls that architects and programmers have for customizing the behavior of the OS. Included is a discussion of some of the debugging tools that are often shipped with OSes.

The promise and challenges of multicore arise out of the concept of concurrency. Without concurrency, multicore is no better than a single core. The implications of concurrency both for faster program execution and for mind-numbing debugging are at the same time profound and subtle. Because everything that’s important about multicore relates to concurrency, this chapter tackles the topic at a high level. It presents some of the obvious aspects of attempts to run multiple tasks at the same time, but also introduces the many complications and difficulties that accompany thel benefits.

One of the hardest parts of the process of migrating from single-core to multicore is making programs that used to work well on single-core architectures work correctly, but more quickly, on a new multicore architecture. Careless partitioning of a sequential program can result in subtle, hard-to-detect bugs – some of which may not even be reliably repeatable. This chapter discusses first why it is that such problems occur, and then how to deal with it. The challenge is that solving this problem through manual techniques alone is enormously difficult. But tools have been developed that help with some of the more difficult aspects of program partitioning, so the chapter concludes with a discussion of those tools.

The performance of critical compute-intensive operations in embedded systems can be significantly improved by replacing software execution with hardware accelerators. Depending on how this is done, however, it may add concurrency even to a single-core system. This chapter discusses the different ways in which hardware accelerators can be designed and managed, and how the opportunity for concurrency can be exploited while avoiding the possible pitfalls of parallel execution.

Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. Discusses the available programming models spread across different abstraction levels The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as: Architectures and interconnects Embedded design methodologies Mapping of applications

This chapter presents several different programming languages suitable for developing applications for multicore embedded systems. Writing programs for embedded systems can be very different from writing programs for general-purpose computers. Embedded systems may have resource limitations such as processing and battery power, memory, input/output capabilities and limited operating system functionality. They may have real-time and safety considerations that need to be met. In addition, developing for multicore embedded systems requires the programming language to provide concurrency support. In this chapter, special emphasis is placed on demonstrating features of each language that support efficient development on multicore embedded systems.

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015. The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

The proliferation of multicore processors in the embedded market for Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) makes developing real-time embedded applications increasingly difficult. What is the underlying theory that makes multicore real-time possible? How does theory influence application design? When is a real-time operating system (RTOS) useful? What RTOS features do applications need? How does a mature RTOS help manage the complexity of multicore hardware? Real-Time Systems Development with RTEMS and Multicore Processors answers these questions and more with exemplar Real-Time Executive for Multiprocessor Systems (RTEMS) RTOS to provide concrete advice and examples for constructing useful, feature-rich applications. RTEMS is free, open-source software that supports multi-processor systems for over a dozen CPU architectures and over 150 specific system boards in applications spanning the range of IoT and CPS domains such as satellites, particle accelerators, robots, racing motorcycles, building controls, medical devices, and more. The focus of this book is on enabling real-time embedded software engineering while providing sufficient theoretical foundations and hardware background to understand the rationale for key decisions in RTOS and application design and implementation. The topics covered in this book include: Cross-compilation for embedded systems development Concurrent programming models used in real-time embedded software Real-time scheduling theory and algorithms used in wide practice Usage and comparison of two application programmer interfaces (APIs) in real-time embedded software: POSIX and the RTEMS Classic APIs Design and implementation in RTEMS of commonly found RTOS features for schedulers, task management, time-keeping, inter-task synchronization, inter-task communication, and networking The challenges introduced by multicore hardware, advances in multicore real-time theory, and software engineering multicore real-time systems with RTEMS All the authors of this book are experts in the academic field of real-time embedded systems. Two of the authors are primary open-source maintainers of the RTEMS software project.