Architecture Design for Soft Errors

Architecture Design for Soft Errors
Author: Shubu Mukherjee
Publsiher: Morgan Kaufmann Pub
Total Pages: 337
Release: 2008
ISBN 10: 9780123695291
ISBN 13: 0123695295
Language: EN, FR, DE, ES & NL

Architecture Design for Soft Errors Book Review:

This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem deffinition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. TABLE OF CONTENTS Chapter 1: Introduction Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation Chapter 3: Architectural Vulnerability Analysis Chapter 4: Advanced Architectural Vulnerability Analysis Chapter 5: Error Coding Techniques Chapter 6: Fault Detection via Redundant Execution Chapter 7: Hardware Error Recovery Chapter 8: Software Detection and Recovery * Provides the methodologies necessary to quantify the effect of radiation-induced soft errors as well as state-of-the-art techniques to protect against them

Architecture Design for Soft Errors

Architecture Design for Soft Errors
Author: Shubu Mukherjee
Publsiher: Morgan Kaufmann
Total Pages: 360
Release: 2011-08-29
ISBN 10: 9780080558325
ISBN 13: 0080558321
Language: EN, FR, DE, ES & NL

Architecture Design for Soft Errors Book Review:

Architecture Design for Soft Errors provides a comprehensive description of the architectural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem definition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. There are a number of different ways this book can be read or used in a course: as a complete course on architecture design for soft errors covering the entire book; a short course on architecture design for soft errors; and as a reference book on classical fault-tolerant machines. This book is recommended for practitioners in semi-conductor industry, researchers and developers in computer architecture, advanced graduate seminar courses on soft errors, and (iv) as a reference book for undergraduate courses in computer architecture. Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors Shows readers how to quantify their soft error reliability Provides state-of-the-art techniques to protect against soft errors

Soft Errors

Soft Errors
Author: Jean-Luc Autran,Daniela Munteanu
Publsiher: CRC Press
Total Pages: 439
Release: 2015-02-25
ISBN 10: 146659084X
ISBN 13: 9781466590847
Language: EN, FR, DE, ES & NL

Soft Errors Book Review:

Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most important primary limits for modern digital electronic reliability. Covering the fundamentals of soft errors as well as engineering considerations and technological aspects, this robust text: Discusses the basics of the natural radiation environment, particle interactions with matter, and soft-error mechanisms Details instrumentation developments in the fields of environment characterization, particle detection, and real-time and accelerated tests Describes the latest computational developments, modeling, and simulation strategies for the soft error-rate estimation in digital circuits Explores trends for future technological nodes and emerging devices Soft Errors: From Particles to Circuits presents the state of the art of this complex subject, providing comprehensive knowledge of the complete chain of the physics of soft errors. The book makes an ideal text for introductory graduate-level courses, offers academic researchers a specialized overview, and serves as a practical guide for semiconductor industry engineers or application engineers.

Soft Errors

Soft Errors
Author: Jean-Luc Autran,Daniela Munteanu
Publsiher: CRC Press
Total Pages: 439
Release: 2017-12-19
ISBN 10: 1351831550
ISBN 13: 9781351831550
Language: EN, FR, DE, ES & NL

Soft Errors Book Review:

Soft errors are a multifaceted issue at the crossroads of applied physics and engineering sciences. Soft errors are by nature multiscale and multiphysics problems that combine not only nuclear and semiconductor physics, material sciences, circuit design, and chip architecture and operation, but also cosmic-ray physics, natural radioactivity issues, particle detection, and related instrumentation. Soft Errors: From Particles to Circuits addresses the problem of soft errors in digital integrated circuits subjected to the terrestrial natural radiation environment—one of the most important primary limits for modern digital electronic reliability. Covering the fundamentals of soft errors as well as engineering considerations and technological aspects, this robust text: Discusses the basics of the natural radiation environment, particle interactions with matter, and soft-error mechanisms Details instrumentation developments in the fields of environment characterization, particle detection, and real-time and accelerated tests Describes the latest computational developments, modeling, and simulation strategies for the soft error-rate estimation in digital circuits Explores trends for future technological nodes and emerging devices Soft Errors: From Particles to Circuits presents the state of the art of this complex subject, providing comprehensive knowledge of the complete chain of the physics of soft errors. The book makes an ideal text for introductory graduate-level courses, offers academic researchers a specialized overview, and serves as a practical guide for semiconductor industry engineers or application engineers.

Soft Errors in Modern Electronic Systems

Soft Errors in Modern Electronic Systems
Author: Michael Nicolaidis
Publsiher: Springer Science & Business Media
Total Pages: 318
Release: 2010-09-24
ISBN 10: 9781441969934
ISBN 13: 1441969934
Language: EN, FR, DE, ES & NL

Soft Errors in Modern Electronic Systems Book Review:

This book provides a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modelling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device-level, cell-level, circuit-level, architectural-level, software level and system level soft error mitigation techniques. The book contains a comprehensive presentation of most recent advances on understanding, qualifying and mitigating the soft error effect in advanced electronic systems, presented by academia and industry experts in reliability, fault tolerance, EDA, processor, SoC and system design, and in particular, experts from industries that have faced the soft error impact in terms of product reliability and related business issues and were in the forefront of the countermeasures taken by these companies at multiple levels in order to mitigate the soft error effects at a cost acceptable for commercial products. In a fast moving field, where the impact on ground level electronics is very recent and its severity is steadily increasing at each new process node, impacting one after another various industry sectors (as an example, the Automotive Electronics Council comes to publish qualification requirements on soft errors), research and technology developments and industrial practices have evolve very fast, outdating the most recent books edited at 2004.

Soft Error Reliability of VLSI Circuits

Soft Error Reliability of VLSI Circuits
Author: Behnam Ghavami,Mohsen Raji
Publsiher: Springer Nature
Total Pages: 114
Release: 2020-11-14
ISBN 10: 3030516105
ISBN 13: 9783030516109
Language: EN, FR, DE, ES & NL

Soft Error Reliability of VLSI Circuits Book Review:

This book is intended for readers who are interested in the design of robust and reliable electronic digital systems. The authors cover emerging trends in design of today’s reliable electronic systems which are applicable to safety-critical applications, such as automotive or healthcare electronic systems. The emphasis is on modeling approaches and algorithms for analysis and mitigation of soft errors in nano-scale CMOS digital circuits, using techniques that are the cornerstone of Computer Aided Design (CAD) of reliable VLSI circuits. The authors introduce software tools for analysis and mitigation of soft errors in electronic systems, which can be integrated easily with design flows. In addition to discussing soft error aware analysis techniques for combinational logic, the authors also describe new soft error mitigation strategies targeting commercial digital circuits. Coverage includes novel Soft Error Rate (SER) analysis techniques such as process variation aware SER estimation and GPU accelerated SER analysis techniques, in addition to SER reduction methods such as gate sizing and logic restructuring based SER techniques.

VLSI SoC Research Trends in VLSI and Systems on Chip

VLSI SoC  Research Trends in VLSI and Systems on Chip
Author: Giovanni De Micheli,Salvador Mir,Ricardo Reis
Publsiher: Springer
Total Pages: 394
Release: 2010-08-23
ISBN 10: 0387749098
ISBN 13: 9780387749099
Language: EN, FR, DE, ES & NL

VLSI SoC Research Trends in VLSI and Systems on Chip Book Review:

This book contains extended and revised versions of the best papers presented during the fourteenth IFIP TC 10/WG 10.5 International Conference on Very Large Scale Integration. This conference provides a forum to exchange ideas and show industrial and academic research results in microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels.

Fault Tolerant Computer Architecture

Fault Tolerant Computer Architecture
Author: Daniel Sorin
Publsiher: Morgan & Claypool Publishers
Total Pages: 104
Release: 2009-07-08
ISBN 10: 1598299549
ISBN 13: 9781598299540
Language: EN, FR, DE, ES & NL

Fault Tolerant Computer Architecture Book Review:

For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future

Achieving High Availability with Commodity Hardware and Software

Achieving High Availability with Commodity Hardware and Software
Author: Nidhi Aggarwal
Publsiher: Unknown
Total Pages: 118
Release: 2008
ISBN 10:
ISBN 13: WISC:89100582303
Language: EN, FR, DE, ES & NL

Achieving High Availability with Commodity Hardware and Software Book Review:

FPGAs and Parallel Architectures for Aerospace Applications

FPGAs and Parallel Architectures for Aerospace Applications
Author: Fernanda Kastensmidt,Paolo Rech
Publsiher: Springer
Total Pages: 325
Release: 2015-12-07
ISBN 10: 3319143522
ISBN 13: 9783319143521
Language: EN, FR, DE, ES & NL

FPGAs and Parallel Architectures for Aerospace Applications Book Review:

This book introduces the concepts of soft errors in FPGAs, as well as the motivation for using commercial, off-the-shelf (COTS) FPGAs in mission-critical and remote applications, such as aerospace. The authors describe the effects of radiation in FPGAs, present a large set of soft-error mitigation techniques that can be applied in these circuits, as well as methods for qualifying these circuits under radiation. Coverage includes radiation effects in FPGAs, fault-tolerant techniques for FPGAs, use of COTS FPGAs in aerospace applications, experimental data of FPGAs under radiation, FPGA embedded processors under radiation and fault injection in FPGAs. Since dedicated parallel processing architectures such as GPUs have become more desirable in aerospace applications due to high computational power, GPU analysis under radiation is also discussed.

Soft error Mitigation at the Architecture level Using Berger Codes for Error Detection

Soft error Mitigation at the Architecture level Using Berger Codes for Error Detection
Author: Edward John Ossi
Publsiher: Unknown
Total Pages: 54
Release: 2011
ISBN 10:
ISBN 13: OCLC:768230413
Language: EN, FR, DE, ES & NL

Soft error Mitigation at the Architecture level Using Berger Codes for Error Detection Book Review:

Resistive Random Access Memory RRAM

Resistive Random Access Memory  RRAM
Author: Shimeng Yu
Publsiher: Morgan & Claypool Publishers
Total Pages: 79
Release: 2016-03-18
ISBN 10: 162705930X
ISBN 13: 9781627059305
Language: EN, FR, DE, ES & NL

Resistive Random Access Memory RRAM Book Review:

RRAM technology has made significant progress in the past decade as a competitive candidate for the next generation non-volatile memory (NVM). This lecture is a comprehensive tutorial of metal oxide-based RRAM technology from device fabrication to array architecture design. State-of-the-art RRAM device performances, characterization, and modeling techniques are summarized, and the design considerations of the RRAM integration to large-scale array with peripheral circuits are discussed. Chapter 2 introduces the RRAM device fabrication techniques and methods to eliminate the forming process, and will show its scalability down to sub-10 nm regime. Then the device performances such as programming speed, variability control, and multi-level operation are presented, and finally the reliability issues such as cycling endurance and data retention are discussed. Chapter 3 discusses the RRAM physical mechanism, and the materials characterization techniques to observe the conductive filaments and the electrical characterization techniques to study the electronic conduction processes. It also presents the numerical device modeling techniques for simulating the evolution of the conductive filaments as well as the compact device modeling techniques for circuit-level design. Chapter 4 discusses the two common RRAM array architectures for large-scale integration: one-transistor-one-resistor (1T1R) and cross-point architecture with selector. The write/read schemes are presented and the peripheral circuitry design considerations are discussed. Finally, a 3D integration approach is introduced for building ultra-high density RRAM array. Chapter 5 is a brief summary and will give an outlook for RRAM’s potential novel applications beyond the NVM applications.

Software Architecture in Practice

Software Architecture in Practice
Author: Len Bass,Paul Clements,Rick Kazman
Publsiher: Addison-Wesley Professional
Total Pages: 528
Release: 2003
ISBN 10: 9780321154958
ISBN 13: 0321154959
Language: EN, FR, DE, ES & NL

Software Architecture in Practice Book Review:

This is the eagerly-anticipated revision to one of the seminal books in the field of software architecture which clearly defines and explains the topic.

Design and Test Technology for Dependable Systems on chip

Design and Test Technology for Dependable Systems on chip
Author: Raimund Ubar,Jaan Raik,Heinrich Theodor Vierhaus
Publsiher: IGI Global
Total Pages: 550
Release: 2011-01-01
ISBN 10: 1609602145
ISBN 13: 9781609602147
Language: EN, FR, DE, ES & NL

Design and Test Technology for Dependable Systems on chip Book Review:

"This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

On Line Testing Workshop

On Line Testing Workshop
Author: Anonim
Publsiher: IEEE
Total Pages: 273
Release: 2002
ISBN 10: 9780769516417
ISBN 13: 0769516416
Language: EN, FR, DE, ES & NL

On Line Testing Workshop Book Review:

This text contains information on computer engineering as presented at the 8th IEEE International On-Line Testing Workshop (IOLTW 2002).

Software Implemented Hardware Fault Tolerance

Software Implemented Hardware Fault Tolerance
Author: Olga Goloubeva,Maurizio Rebaudengo,Matteo Sonza Reorda,Massimo Violante
Publsiher: Springer Science & Business Media
Total Pages: 228
Release: 2006-09-19
ISBN 10: 0387329374
ISBN 13: 9780387329376
Language: EN, FR, DE, ES & NL

Software Implemented Hardware Fault Tolerance Book Review:

This book presents the theory behind software-implemented hardware fault tolerance, as well as the practical aspects needed to put it to work on real examples. By evaluating accurately the advantages and disadvantages of the already available approaches, the book provides a guide to developers willing to adopt software-implemented hardware fault tolerance in their applications. Moreover, the book identifies open issues for researchers willing to improve the already available techniques.

Dependability in Electronic Systems

Dependability in Electronic Systems
Author: Nobuyasu Kanekawa,Eishi H. Ibe,Takashi Suga,Yutaka Uematsu
Publsiher: Springer Science & Business Media
Total Pages: 204
Release: 2010-11-08
ISBN 10: 9781441967152
ISBN 13: 144196715X
Language: EN, FR, DE, ES & NL

Dependability in Electronic Systems Book Review:

This book covers the practical application of dependable electronic systems in real industry, such as space, train control and automotive control systems, and network servers/routers. The impact from intermittent errors caused by environmental radiation (neutrons and alpha particles) and EMI (Electro-Magnetic Interference) are introduced together with their most advanced countermeasures. Power Integration is included as one of the most important bases of dependability in electronic systems. Fundamental technical background is provided, along with practical design examples. Readers will obtain an overall picture of dependability from failure causes to countermeasures for their relevant systems or products, and therefore, will be able to select the best choice for maximum dependability.

Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures

Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures
Author: Pavan Kamal Sudheendra Poluri
Publsiher: Unknown
Total Pages: 147
Release: 2014
ISBN 10:
ISBN 13: OCLC:903490369
Language: EN, FR, DE, ES & NL

Fault Tolerant Network on Chip Router Architectures for Multi Core Architectures Book Review:

As the feature size scales down to deep nanometer regimes, it has enabled the designers to fabricate chips with billions of transistors. The availability of such abundant computational resources on a single chip has made it possible to design chips with multiple computational cores, resulting in the inception of Chip Multiprocessors (CMPs). The widespread use of CMPs has resulted in a paradigm shift from computation-centric architectures to communication-centric architectures. With the continuous increase in the number of cores that can be fabricated on a single chip, communication between the cores has become a crucial factor in its overall performance. Network-on-Chip (NoC) paradigm has evolved into a standard on-chip interconnection network that can efficiently handle the strict communication requirements between the cores on a chip. The components of an NoC include routers, that facilitate routing of data between multiple cores and links that provide raw bandwidth for data traversal. While diminishing feature size has made it possible to integrate billions of transistors on a chip, the advantage of multiple cores has been marred with the waning reliability of transistors. Components of an NoC are not immune to the increasing number of hard faults and soft errors emanating due to extreme miniaturization of transistor sizes. Faults in an NoC result in significant ramifications such as isolation of healthy cores, deadlock, data corruption, packet loss and increased packet latency, all of which have a severe impact on the performance of a chip. This has stimulated the need to design resilient and fault tolerant NoCs. This thesis handles the issue of fault tolerance in NoC routers. Within the NoC router, the focus is specifically on the router pipeline that is responsible for the smooth flow of packets. In this thesis we propose two different fault tolerant architectures that can continue to operate in the presence of faults. In addition to these two architectures, we also propose a new reliability metric for evaluating soft error tolerant techniques targeted towards the control logic of the NoC router pipeline. First, we present Shield, a fault tolerant NoC router architecture that is capable of handling both hard faults and soft errors in its pipeline. Shield uses techniques such as spatial redundancy, exploitation of idle resources and bypassing a faulty resource to achieve hard fault tolerance. The use of these techniques reveals that Shield is six times more reliable than baseline-unprotected router. To handle soft errors, Shield uses selective hardening technique that includes hardening specific gates of the router pipeline to increase its soft error tolerance. To quantify soft error tolerance improvement, we propose a new metric called Soft Error Improvement Factor (SEIF) and use it to show that Shield's soft error tolerance is three times better than that of the baseline-unprotected router. Then, we present Soft Error Tolerant NoC Router (STNR), a low overhead fault tolerating NoC router architecture that can tolerate soft errors in the control logic of its pipeline. STNR achieves soft error tolerance based on the idea of dual execution, comparison and rollback. It exploits idle cycles in the router pipeline to perform redundant computation and comparison necessary for soft error detection. Upon the detection of a soft error, the pipeline is rolled back to the stage that got affected by the soft error. Salient features of STNR include high level of soft error detection, fault containment and minimum impact on latency. Simulations show that STNR has been able to detect all injected single soft errors in the router pipeline. To perform a quantitative comparison between STNR and other existing similar architectures, we propose a new reliability metric called Metric for Soft error Tolerance (MST) in this thesis. MST is unique in the aspect that it encompasses four crucial factors namely, soft error tolerance, area overhead, power overhead and pipeline latency overhead into a single metric. Analysis using MST shows that STNR provides better reliability while incurring low overhead compared to existing architectures.

Solutions Architect s Handbook

Solutions Architect s Handbook
Author: Saurabh Shrivastava,Neelanjali Srivastav
Publsiher: Packt Publishing Ltd
Total Pages: 490
Release: 2020-03-21
ISBN 10: 183864783X
ISBN 13: 9781838647834
Language: EN, FR, DE, ES & NL

Solutions Architect s Handbook Book Review:

This book will show you how to create robust, scalable, highly available and fault-tolerant solutions by learning different aspects of Solution architecture and next-generation architecture design in the Cloud environment.

Designing Data Intensive Applications

Designing Data Intensive Applications
Author: Martin Kleppmann
Publsiher: "O'Reilly Media, Inc."
Total Pages: 616
Release: 2017-03-16
ISBN 10: 1491903104
ISBN 13: 9781491903100
Language: EN, FR, DE, ES & NL

Designing Data Intensive Applications Book Review:

Data is at the center of many challenges in system design today. Difficult issues need to be figured out, such as scalability, consistency, reliability, efficiency, and maintainability. In addition, we have an overwhelming variety of tools, including relational databases, NoSQL datastores, stream or batch processors, and message brokers. What are the right choices for your application? How do you make sense of all these buzzwords? In this practical and comprehensive guide, author Martin Kleppmann helps you navigate this diverse landscape by examining the pros and cons of various technologies for processing and storing data. Software keeps changing, but the fundamental principles remain the same. With this book, software engineers and architects will learn how to apply those ideas in practice, and how to make full use of data in modern applications. Peer under the hood of the systems you already use, and learn how to use and operate them more effectively Make informed decisions by identifying the strengths and weaknesses of different tools Navigate the trade-offs around consistency, scalability, fault tolerance, and complexity Understand the distributed systems research upon which modern databases are built Peek behind the scenes of major online services, and learn from their architectures